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4H-SiC Pseudo-CMOS Logic Inverters for Harsh Environment Electronics
https://repo.qst.go.jp/records/48704
https://repo.qst.go.jp/records/48704c1353289-c670-4171-a424-a52fbaded103
| Item type | 学術雑誌論文 / Journal Article(1) | |||||
|---|---|---|---|---|---|---|
| 公開日 | 2018-04-12 | |||||
| タイトル | ||||||
| タイトル | 4H-SiC Pseudo-CMOS Logic Inverters for Harsh Environment Electronics | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| 資源タイプ | ||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
| 資源タイプ | journal article | |||||
| アクセス権 | ||||||
| アクセス権 | metadata only access | |||||
| アクセス権URI | http://purl.org/coar/access_right/c_14cb | |||||
| 著者 |
Kuroki, Shin-ichiro
× Kuroki, Shin-ichiro× Kurose, T.× Nagatsuma, H.× Ishikawa, S.× Maeda, T.× Sezaki, H.× Kikkawa, T.× Makino, T.× Ohshima, T.× Ostling, M.× Zetterling, C.-M.× 牧野 高紘× 大島 武 |
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| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | Summary form only given. The complete presentation was not made available for publication as part of the conference proceedings. For logic gate with higher voltage swing, 4H-SiC pseudo-CMOS logic inverter with four nMOS was suggested and demonstrated, and a high voltage swing of 4.4 V was achieved at VDD=5 V. Simple nMOS inverters were also investigated. Both of pseudo-CMOS and nMOS inverters were operated at a high temperature of 200°C. For future SiC large integrated circuits, junction leakage current between n+ regions were also investigated with the comb-shaped test elements. | |||||
| 書誌情報 |
Materials Science Forum 巻 897, p. 669-672, 発行日 2017-02 |
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| ISSN | ||||||
| 収録物識別子タイプ | ISSN | |||||
| 収録物識別子 | 0255-5476 | |||||
| DOI | ||||||
| 識別子タイプ | DOI | |||||
| 関連識別子 | 10.4028/www.scientific.net/MSF.897.669 | |||||
