@article{oai:repo.qst.go.jp:00048704,
 author = {Kuroki, Shin-ichiro and Kurose, T. and Nagatsuma, H. and Ishikawa, S. and Maeda, T. and Sezaki, H. and Kikkawa, T. and Makino, T. and Ohshima, T. and Ostling, M. and Zetterling, C.-M. and 牧野 高紘 and 大島 武},
 journal = {Materials Science Forum},
 month = {Feb},
 note = {Summary form only given. The complete presentation was not made available for publication as part of the conference proceedings. For logic gate with higher voltage swing, 4H-SiC pseudo-CMOS logic inverter with four nMOS was suggested and demonstrated, and a high voltage swing of 4.4 V was achieved at VDD=5 V. Simple nMOS inverters were also investigated. Both of pseudo-CMOS and nMOS inverters were operated at a high temperature of 200°C. For future SiC large integrated circuits, junction leakage current between n+ regions were also investigated with the comb-shaped test elements.},
 pages = {669--672},
 title = {4H-SiC Pseudo-CMOS Logic Inverters for Harsh Environment Electronics},
 volume = {897},
 year = {2017}
}