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Low-Parasitic-Capacitance Self-Aligned 4H-SiC nMOSFETs for Harsh Environment Electronics
https://repo.qst.go.jp/records/49123
https://repo.qst.go.jp/records/49123ab293afe-f105-424c-86f5-213b427be617
| Item type | 学術雑誌論文 / Journal Article(1) | |||||
|---|---|---|---|---|---|---|
| 公開日 | 2018-08-02 | |||||
| タイトル | ||||||
| タイトル | Low-Parasitic-Capacitance Self-Aligned 4H-SiC nMOSFETs for Harsh Environment Electronics | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| 資源タイプ | ||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
| 資源タイプ | journal article | |||||
| アクセス権 | ||||||
| アクセス権 | metadata only access | |||||
| アクセス権URI | http://purl.org/coar/access_right/c_14cb | |||||
| 著者 |
Kurose, T.
× Kurose, T.× Kuroki, S.-I.× Ishikawa, S.× Maeda, T.× Sezaki, H.× Makino, Takahiro× Ohshima, Takeshi× Östling, M.× Zetterling, C.-M.× 牧野 高紘× 大島 武 |
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| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | Low-parasitic-capacitance 4H-SiC nMOSFETs using a novel self-aligned process were demonstrated. In these nMOSFETs, device characteristics including parasitic capacitance (gate-source, gate-drain, drain-source capacitance) were investigated. As a result, low parasitic capacitance was achieved by the self-aligned structure. | |||||
| 書誌情報 |
Materials Science Forum 巻 924, p. 971-974, 発行日 2018-06 |
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| 出版者 | ||||||
| 出版者 | Trans Tech Publications | |||||
| DOI | ||||||
| 識別子タイプ | DOI | |||||
| 関連識別子 | 10.4028/www.scientific.net/MSF.924.971 | |||||
