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FPGA-based interlock system for the chopper of the Linear IFMIF prototype accelerator injector
https://repo.qst.go.jp/records/77712
https://repo.qst.go.jp/records/77712d8aab898-16f4-4789-80d6-2a9f39511aed
| Item type | 学術雑誌論文 / Journal Article(1) | |||||
|---|---|---|---|---|---|---|
| 公開日 | 2019-11-28 | |||||
| タイトル | ||||||
| タイトル | FPGA-based interlock system for the chopper of the Linear IFMIF prototype accelerator injector | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| 資源タイプ | ||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
| 資源タイプ | journal article | |||||
| アクセス権 | ||||||
| アクセス権 | metadata only access | |||||
| アクセス権URI | http://purl.org/coar/access_right/c_14cb | |||||
| 著者 |
Astrain, M.
× Astrain, M.× Barrera, E.× A., Carpeño× Hirata, Yosuke× Kasugai, Atsushi× Marqueta, A.× Sanz, D.× Jugo, J.× Badillo, I.× Yosuke, Hirata× Atsushi, Kasugai |
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| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | he Linear IFMIF (International Fusion Materials Irradiation Facility) Prototype Accelerator (LIPAc) injector consists of a 140 mA proton/deuteron source, its associated low energy beam transport line (LEBT) as well as ancillaries such as water cooling skid, vacuum groups, High Voltage Power Supplies (HVPS), etc. A specific element, the beam “Chopper”, was included in the LEBT to generate short (˜ 100μs) and sharp-edged beam pulses (˜10μs) and allow the use of interceptive diagnostics in the high energy part of the LIPAc during commissioning phases of the Radio Frequency Quadrupole RFQ (5 MeV) and the Superconducting Radio Frequency SRF Linac (9 MeV). The chopper was designed to operate in pulsed mode with very sharp rise and fall times, meaning the chopper will be used to “cut” the long rise time of the source as well as the fall time of the beam pulse. The chopper thermal screen has not been designed to withstand very high beam power (i.e., beam length and duty cycle need to be monitored); in addition, the chopper HVPS needs to be monitored in real time to detect a possible trip and extract the beam before downstream devices are damaged. For these applications, standard PLC based interlocks are too slow; therefore, faster solutions are envisaged. The proposed solution for the required interlock system is based on COTS technology with XILINX FPGAs using RIO (Reconfigurable Input/Output) technology from National Instruments (CompactRIO platform). The paper discusses the implementation of the interlock system, the response times of the proposed architecture and the fitness of the technology. Additionally, the system can be integrated into the IFMIF control system using EPICS as a standalone solution. |
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| 書誌情報 |
Fusion Engineering and Design 巻 146, 号 B, p. 1708-1711, 発行日 2019-11 |
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| 出版者 | ||||||
| 出版者 | Elsevier | |||||
| ISSN | ||||||
| 収録物識別子タイプ | ISSN | |||||
| 収録物識別子 | 0920-3796 | |||||
| DOI | ||||||
| 識別子タイプ | DOI | |||||
| 関連識別子 | 10.1016/j.fusengdes.2019.03.021 | |||||
| 関連サイト | ||||||
| 識別子タイプ | URI | |||||
| 関連識別子 | https://www.sciencedirect.com/science/article/pii/S0920379619303424 | |||||
