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Design and Engineering of Ga2O3 MOSFETs for Next Generation Power Switches
https://repo.qst.go.jp/records/73319
https://repo.qst.go.jp/records/73319a4d5a1e0-6502-4570-8acc-e7136b41ed50
| Item type | 会議発表用資料 / Presentation(1) | |||||
|---|---|---|---|---|---|---|
| 公開日 | 2018-03-24 | |||||
| タイトル | ||||||
| タイトル | Design and Engineering of Ga2O3 MOSFETs for Next Generation Power Switches | |||||
| 言語 | ||||||
| 言語 | jpn | |||||
| 資源タイプ | ||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_c94f | |||||
| 資源タイプ | conference object | |||||
| アクセス権 | ||||||
| アクセス権 | metadata only access | |||||
| アクセス権URI | http://purl.org/coar/access_right/c_14cb | |||||
| 著者 |
Hoi, Wong Man
× Hoi, Wong Man× Nakata, Yoshiaki× Sasaki, Kohei× Morikawa, Yoji× Takeyama, Akinori× 牧野, 高紘× 大島, 武× Kuramata, Akito× Yamakoshi, Shigenobu× 武山 昭憲× 牧野 高紘× 大島 武 |
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| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | β-Ga2O3 is being actively pursued for power switching and harsh environment electronics owing to its large bandgap of 4.5 eV and the availability of economical melt-grown native substrates. State-of-the-art Ga2O3 MOSFETs were realized on unintentionally-doped (UID) β-Ga2O3 (010) epilayers by employing Si-ion (Si+) implantation doping for the channel and ohmic contacts. Depletion-mode devices with a gate-connected field plate (FP) achieved a high off-state breakdown voltage of 755 V, a large drain current on/off ratio (ION/IOFF) of over 109, stable high temperature operation at 300°C, and dispersion-free pulsed output characteristics. Bulk Ga2O3 exhibited high gamma-ray tolerance by virtue of the MOSFETs’stable DC characteristics against irradiation, while radiation-induced dielectric damage and interface trap generation limited the overall radiation hardness of these devices. A large thermal resistance of 48 mm·K/W extracted under room temperature device operation highlights the pertinence of thermal management to the performance and reliability of Ga2O3 transistors. Low residual carrier density in UID Ga2O3 enabled full channel depletion at zero gate bias for a positive threshold voltage in Si+-implanted enhancement-mode β-Ga2O3 (010) MOSFETs with low series resistance. Despite strong charge trapping effects associated with an unoptimized gate dielectric, a decent ION of 1.4 mA/mm and large ION/IOFF near 106 were achieved. | |||||
| 会議概要（会議名, 開催地, 会期, 主催者等） | ||||||
| 内容記述タイプ | Other | |||||
| 内容記述 | The Tenth International Conference on the Science and Technology for Advanced Ceramics (STAC-10) | |||||
| 発表年月日 | ||||||
| 日付 | 2017-08-01 | |||||
| 日付タイプ | Issued | |||||
