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Synchronized Clock System for Acceleration Pattern Generation and its Beam Tests in HIMAC Synchrotron
https://repo.qst.go.jp/records/70139
https://repo.qst.go.jp/records/701392dbf354d-2a83-483e-a8f5-b1096ade90bc
Item type | 会議発表用資料 / Presentation(1) | |||||
---|---|---|---|---|---|---|
公開日 | 2010-06-01 | |||||
タイトル | ||||||
タイトル | Synchronized Clock System for Acceleration Pattern Generation and its Beam Tests in HIMAC Synchrotron | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_c94f | |||||
資源タイプ | conference object | |||||
アクセス権 | ||||||
アクセス権 | metadata only access | |||||
アクセス権URI | http://purl.org/coar/access_right/c_14cb | |||||
著者 |
Kanazawa, Mitsutaka
× Kanazawa, Mitsutaka× et.al× 金澤 光隆 |
|||||
抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | In the routine operation of HIMAC synchrotron, a pulse system of field change with 0.2 Gauss in the monitor dipole magnet (B-clock) is used to generate pattern data in the acceleration system. To eliminate error pulse due to noise in analogue field signal, a clock system locked to a 1.2kHz clock for a power supplies was developed, which can be used to generate pattern data of an acceleration system with maximum frequency of 192kHz. Because the 1.2kHz clock is synchronized to a power line | |||||
会議概要(会議名, 開催地, 会期, 主催者等) | ||||||
内容記述タイプ | Other | |||||
内容記述 | IPAC10 | |||||
発表年月日 | ||||||
日付 | 2010-05-28 | |||||
日付タイプ | Issued |